This article is part of TechXchange: RISC-V: The Instruction Set Alternative.
SiFivea startup providing IP based on the RISC-V architecture, says NASA selected it to provide the main processor for the agency’s next high-performance spaceflight processor, a big win for the instruction set emerge.
While SiFive will provide RISC-V processor cores for the program, the space agency has inked the American company Microchip technology to a $50 million contract to create the High Performance Space Flight Computer (HPSC). The chip is designed for high-level missions, including spacecraft for planetary exploration and future manned missions to the Moon and Mars. Microchip said it would take three years to complete the work.
For NASA, the chips are intended to replace the PowerPC-based space processor that has been used in spacecraft ranging from the Curiosity and Perseverance rovers at the new James Webb Space Telescope.
At the processor’s core will be a vector-optimized SiFive X280 RISC-V eight-core processor, along with four general-purpose RISC-V processor cores, giving it a 100x performance improvement over its predecessor. .
The huge generational leap in performance will help unlock new possibilities for everything from spaceflight and guidance systems to autonomous rovers, vision processing and communications, SiFive said.
Low risk with RISC-V
While RISC-V is an open instruction set architecture (ISA), SiFive is building a business by designing RISC-V processor cores and offering them to other companies, which combine them with other IPs in systems on a chip (SoC).
RISC-V is an open standard supported by a number of companies around the world. This contrasts with closed, proprietary architectures like Arm and Intel’s x86, subject to the whims of a single company, said Jack Kang, senior vice president of business development at SiFive.
Bonus points: companies and countries aren’t locked into a single company for their entire roadmap and lifecycle, relying on Arm and Intel to continue research and development.
Although RISC-V technology is becoming more widespread, it is still the new block architecture. But it’s part of why SiFive thinks it’s the perfect fit for a platform that will remain in use at NASA for decades.
But according to Kang, the RISC-V architecture is a safe bet for NASA. Although the ecosystem around RISC-V is still in its early stages of growth, it is growing rapidly.
Since NASA plans to use the space-grade processor for decades, “choosing an architecture that will enjoy long-term support and growth is critical,” he stressed. “Which architecture will have the most engineers, programmers and ecosystem in 5, 10, 15 years? The previous space computer was based on a proprietary PowerPC, developed 20 years ago – and look where that architecture stands today.
RISC-V, a reduced instruction set computer (RISC) architecture similar to Arm, is also gaining a foothold in US universities, providing the nation with a growing talent base who will know how to use it, Kang said.
“When you look at it that way, choosing the RISC-V ISA becomes [the] obvious winner.
The open nature of RISC-V means that everyone, from semiconductor industry leaders to researchers, has the freedom to contribute. Kang said, “The opening of RISC-V also brings a very large ecosystem of software developers, open source communities, [and] commercial sellers. They all now have the ability to write software that will be used in these programs. Now your code, if it is the best, will be used in space.
Spatial Quality Instructions
RISC-V, often compared to Linux in the software world, has firmly established itself as one of the top three ISAs. The architecture has landed hundreds of millions of dollars in investment in recent years, largely due to its open source and free nature. The power of RISC-V is that you can add standard and third-party extensions to increase processor cores, without all the constraints of Arm and x86.
The X280 is built on the 64-bit RISC-V instruction set. SiFive has adapted the RISC-V processor cores by adding vector extensions to give them a boost for digital signal processing (DSP) and artificial intelligence (AI) tasks.
For space-bound workloads, SiFive said the X280 offers several orders of magnitude more performance over competing CPU cores.
As part of the $50 million deal, Microchip will be the one to organize the RISC-V processor cores into a space-grade SoC and surround them with the memory, networking and connectivity required by NASA.
In addition to its speed improvements, the Spatial Processor will offer better power efficiency thanks to its ability to shut down various sections of the SoC when not in use.
The HPSC is also designed to handle the hazards of spaceflight. Chips in satellites and other space systems must withstand violent vibrations and shocks that can cause damage during launch.
In addition, electronics face major thermal management challenges in orbit and further out in space. They must be protected against strong temperature fluctuations which influence their survival time in space.
Radiation hardening is generally required by space chips to preserve their long-term reliability and performance. Radiation damage can lead to the catastrophic failure of processors operating in space.
Under these conditions, commercial processors would not last long before suffering a serious malfunction. Therefore, the emphasis on fault tolerance, radiation hardening and high reliability is another priority for Microchip.
Microchip has provided space-grade chips for years, ranging from radiation-rugged microcontrollers and FPGAs to memory and networking chips for satellites.
The ecosystem grows
This is the latest development in a major year for SiFive. Earlier this year, $175 million was raised in its latest funding round. It is expected to use the funds in part to accelerate development of its most advanced RISC-V processors.
The startup has also partnered with Intel to optimize its leading RISC-V processor IP for the company’s process technology. The move was part of a billion-dollar program funded by Intel to boost its foundry business.
NASA’s decision also marks an important milestone for the RISC-V ecosystem as a whole. The HPSC is designed for use in virtually all future NASA missions, ranging from planetary exploration to lunar and Martian surface missions.
“Each new market segment brings with it more software ecosystem qualities, which are then shared among all other RISC-V ecosystems,” Kang said. NASA’s choice to use RISC-V processor cores in its spaceflight processor further validates RISC-V as a viable alternative to Arm and x86 rivals, he added. It also highlights the performance and power efficiency improvements that companies like SiFive are bringing to the table.
Microchip has announced its intention to offer the new platform to other customers outside of NASA.
Check out more coverage on the RISC-V instruction set architecture here.